1. Field of the Invention
The present invention relates to a semiconductor device such as a half bridge drive circuit. In particular, the invention relates to a semiconductor device having a level shift circuit that transmits an input signal of a low potential system, which is a primary side system, to a high potential system, which is a secondary side system operating on a potential differing from the primary side operating potential, and to a high side circuit drive method.
2. Related Art
To date, a level shift circuit that transmits a low potential system control signal to a high potential system in order to drive a high potential side switching element has been used in a half bridge drive circuit, or the like, to which the power supply voltage of a high potential system power supply is applied.
Hereafter, using FIG. 10, a description will be given of a heretofore known half bridge drive circuit 90.
In FIG. 10, switching elements XD1 and XD2, such as IGBTs, are connected in a totem pole between a power supply potential E and a ground potential GND, configuring a half bridge circuit (an output circuit 10). Also, diodes DH and DL are connected in anti-parallel to the switching elements XD1 and XD2. Further, the configuration is such that an inductive load L1 is connected to a connection point P3 of the switching element XD1 and switching element XD2.
In FIG. 10, the switching element XD1 is an element that, with the potential of the connection point P3 with the switching element XD2 as a reference potential, carries out a switching operation between the reference potential and the power supply potential E, which is supplied by a power supply PS. In the following description, the switching element XD1 will be referred to as a high potential side switching element.
Also, the switching element XD2 is an element that, with the ground potential as a reference potential, carries out a switching operation between the reference potential and the potential of the connection point P3. In the following description, the switching element XD2 will be referred to as a low potential side switching element.
The heretofore known half bridge drive circuit 90 is configured of the output circuit 10 having the switching elements XD1 and XD2, a high side circuit 99 that drives the high potential side switching element XD1, and a low side circuit 30 that drives the low potential side switching element XD2. As the invention relates to the high side circuit, a description of the low side circuit will be omitted.
The high side circuit 99 includes a pulse generator circuit 40 that generates a pulse form set signal (set) and reset signal (reset) for controlling the turning on and off of the high potential side switching element XD1 in response to a low potential system input signal Hdrv provided from a microcomputer, or the like, provided on the exterior but not shown in FIG. 10. The high side circuit 99 also includes level shift circuits 24 and 25 that convert the set signal and reset signal output from the pulse generator circuit 40 to a high potential system signal level, a latch circuit 23 configured of an RS flip-flop, or the like, that latches the level-shifted set signal and reset signal, and a high side driver 21 that generates a gate signal of the high potential side switching element in accordance with the latched signal.
When taking the input signal to be of negative logic and the output signal to be of positive logic, the latch circuit 23 outputs at an H level when the input level-shifted set signal is at an L level (valid) and the level-shifted reset signal is at an H level (invalid), turning on the high potential side switching element XD1 via the high side driver 21, and putting the high potential side switching element XD1 into a conductive state. Also, the latch circuit 23 outputs at an L level when the input level-shifted set signal is at an H level (invalid) and the level-shifted reset signal is at an L level (valid), turning off the high potential side switching element XD1 via the high side driver 21, and putting the high potential side switching element XD1 into a non-conductive state.
When driving the switching elements XD1 and XD2, and supplying power to the inductive load L1, a potential Vs of the connection point P3 fluctuates, which may generate noise occurring because of a temporal change in voltage. In the following description, this noise will be referred to as dV/dt noise.
To date, circuits that combat malfunction due to the dV/dt noise have been proposed. For example, in Japanese Patent No. JP 3,429,937, a latch malfunction protection 22, which is a malfunction prevention circuit, is provided at a stage prior to the latch circuit in order to prevent malfunction of the latch circuit.
The malfunction prevention circuit being of the kind of circuit configuration shown in FIG. 11, when the level-shifted set signal and reset signal are both at an L level (valid), outputs the set signal and reset signal both at an H level (invalid) to the latch circuit 23. As the output of the latch circuit 23 is held because of this, it is possible to prevent malfunction due to dV/dt noise when the level-shifted set signal and reset signal are both transiently at an L level (valid).
However, the potential Vs of the connection point P3 normally rises when the switching element XD1 is switched from an off-state to an on-state and the switching element XD2 is switched from an on-state to an off-state, at which time dV/dt noise is generated. Alternatively, apart from this, the potential Vs may also rise, for example, in a dead time when the switching elements XD1 and XD2 are both in an off-state. This dead time is set in order to prevent a flow-through current from flowing.
That is, when the switching element XD2 is turned on, current flows from the load L1 into the output circuit 10, which is a converter component, and the switching element XD2 is turned off when the switching element XD2 is in a condition such that it is a current sink element, there is no longer a path for the current flowing from the load L1 in the dead time. Because of this, the parasitic capacitance of a potential Vs line connected to the connection point P3 is charged by the current, and the potential Vs rises swiftly. On the potential Vs rising to a voltage such as to turn on the diode DH connected in parallel to the switching element XD1, the diode DH is turned on, and current flows from the load L1 via the diode DH into the power supply PS, causing power loss. The voltage that turns on the diode DH is the sum of the output voltage E of the power supply PS and the forward voltage of the diode DH.
FIGS. 12A-12D show the relationship between the dead time, the output timing of the set signal, and the delay time of an output signal H0 from the high side driver 21.
In FIG. 12D, when a set signal (set-3) changes to an H level after the end of a rise of the potential Vs owing to dead time, or the like, the set signal (set-3) changes to an H level in a condition in which the latch malfunction protection function of the latch malfunction protection circuit 22 is not operating. Because of this, an output signal H0-3 of the high side driver 21 rises, delayed by a unique delay time ta, at the same time as which the switching element XD1 is turned on. The case shown in FIG. 12B where a set signal (set-1) changes to an H level before the rise of the potential Vs also has the same delay time ta.
However, in a case where a set signal (set-2) changes to an H level when the potential Vs is rising due to dead time or the like, that is, in a case where a period in which the potential Vs is rising and the point at which the set signal (set-2) changes to an H-level coincide, a blank period tb longer than the unique delay time ta occurs, as shown in FIG. 12C.
A level-shifted set signal (setdrn-2) and a level-shifted reset signal (resdrn) both change to an L level due to dV/dt noise generated in accompaniment to the rise of the potential Vs shown in FIG. 12C, and the set signal (set-2) changes to an H level while the protection function of the latch malfunction protection circuit 22 is in an operating condition. Because of this, the period in which dV/dt noise is generated ends. Further, the set signal (set-2) is not transmitted to the latch circuit 23 until the latch malfunction protection circuit 22 protection operation period ends. Because of this, an output signal H0-2 of the high side driver 21 rises after a long blank period (tb (>ta)).
As heretofore described, when the potential Vs rises in a dead time period or the like, an operation of turning on the switching element XD1 is delayed because of the blank period tb. Because of this, power loss due to the diode DH connected in parallel to the switching element XD1 becomes a problem. Consequently, there is a demand for technology whereby the switching element XD1 can be turned on as quickly as possible.